Classical inductive impedance transforming devices are unsuitable for application to most semiconductor integrated circuit systems because they are too bulky. Their equivalent electronic circuits are relatively complex and, hence, too costly to implement for many application. Other active electronic circuits that might otherwise be utilized for impedance transformation, such as transistor emitter followers, involve problems such as dealing with transistor junction voltage offsets and relatively large emitter circuit resistors.
In certain systems there is a need to drive digital signals representing a multibit word in parallel from a source latch register with relatively high output impedance to a load with substantially lower output impedance. Such a situation can arise, for example, in circuits for converting between analog and digital signal formats, and in track-hold circuits.
It is known to use a tandem connected chain of transistor switches, such as complementary metal oxide semiconductor (CMOS) transistor switches, for impedance transformation in a single signal transmission path. However, if a plur ality of such switch chains are provided in an impedance transformation matrix such as would be required for multibit signal transmission in parallel signal paths, various transistor characteristics have been found to give rise to usually intolerable differential signal propagation delays among the chains as well as undesirable utilization circuit operating phenomena.